1. Field of the Invention
The present invention relates to a chopper type voltage comparator and a parallel type A/D converter using the same.
2. Description of the Background Art
FIG. 30 is a circuit diagram showing an example of a configuration of a conventional chopper type voltage comparator. As shown in FIG. 30, an input voltage VIN and a reference voltage VREF are connected to one electrode of a capacitor C1 through switches S1 and S2, respectively. The other electrode of the capacitor C1 is connected to the input portion of an inverter INV1. The output portion of the inverter INV1 is connected to one electrode of a capacitor C2 and is also fed back to the input through a switch S3. The other electrode of the capacitor C2 is connected to the input portion of an inverter INV2, whose output portion is connected to the input portion of an inverter INV3 and is also fed back to the input through a switch S4. The output VOUT of the inverter INV3 is provided to a latch circuit 11, and the latch output LOUT from the latch circuit 11 makes the output of the voltage comparator.
FIG. 31 is a circuit diagram showing the configuration in FIG. 30 in more detail. As shown in FIG. 31, the inverters INV1-INV3 each have a CMOS inverter configuration formed of a PMOS transistor QP and an NMOS transistor QN and the switches S1-S4 are each formed of a parallel connection of a PMOS transistor QP and an NMOS transistor QN. A control signal .phi. is applied to the gates of the NMOS transistors QN of the switches S1, S3 and S4 and to the gate of the PMOS transistor QP of the switch S2 and an inverse control signal .phi. is applied to the gates of the PMOS transistors QP of the switches S1, S3 and S4 and to the gate of the NMOS transistor QN of the switch S2.
The latch circuit 11 is formed of switches SL1, SL2 and inverters INV4 and INV5, where the inverters INV4 and INV5 are connected in series, with the switch SL1 interposed between the input portion of the inverter INV4 and the output portion of the inverter INV3 and the switch SL2 interposed between the output portion of the inverter INV5 and the input portion of the inverter INV4. The inverter INV4 and the inverter INV5 each have a CMOS inverter configuration formed of a PMOS transistor QP and an NMOS transistor QN. The switches SL1 and SL2 are each formed of a parallel connection of a PMOS transistor QP and an NMOS transistor QN. The inverse control signal .phi. is applied to the gates of the NMOS transistor QN of the switch SL1 and the PMOS transistor QP of the switch SL2 and the control signal .phi. is applied to the gates of the PMOS transistor QP of the switch SL1 and the NMOS transistor QN of the switch SL2.
With this configuration, the chopper type voltage comparator operates in two phases, a period called auto-zero and a comparison period. FIG. 32 is a diagram for use in describing its operation in the auto-zero period and FIG. 33 is a diagram for use in describing its operation in the comparison period. For convenience, the inverter INV2 and the switch S4 shown in FIG. 30 and FIG. 31 are not shown in these diagrams.
As shown in FIG. 32, in the auto-zero period (AZ period), the control signal .phi. is "H", so the switches S1 and S3 are on and the switch S2 is off. The switch SL1 is off and the switch SL2 is on, and hence the latch circuit 11 comes into a latch state.
In the AZ period, the input voltage VIN of analog form is applied to the one electrode (on the input side) of the capacitor C1 and the input and output of the inverter INV1 are shorted through the switch S3 in an on state, whose input voltage and output voltage match and get stabilized at the bias voltage Vb. As shown in FIG. 34, at the bias voltage Vb, the input voltage and the output voltage of the inverter are equal, with a high gain and a good gain characteristic, which is equal to VDD/2 (VDD: power-supply voltage).
On the other hand, as shown in FIG. 33, in the comparison period (COMP period), the control signal .phi. is "L", and so the switches S1 and S3 are off and the switch S2 is on. The switch SL1 in on and the switch SL2 is off, and hence the latch circuit 11 comes in a through state.
In the COMP period, the reference voltage VREF is applied to the one electrode of the capacitor C1 and the voltage change at this time (VIN.fwdarw.VREF) is transferred to the other electrode of the capacitor C1. In the inverter INV1, since the switch S3 is in an off state at this time, the voltage change on the input side of the inverter INV1 (on the side of the other electrode of the capacitor C1) is superimposed on the bias voltage Vb providing a high gain.
Accordingly, the inverter, having a high gain, detects even a small voltage change of the input, largely amplifies it, and transfers it to the next stage. FIG. 35 (comparison period) shows the change of the operating point at this time. This voltage change is further amplified in the inverter INV3 in the next stage and transferred to the inside of the latch circuit 11.
Subsequently, in the next AZ period, the latch circuit 11 determines the data as "H" or "L." This operation is repeated to compare the input voltage VIN and the reference voltage VREF.
FIG. 36 is a timing diagram showing the above-described comparing operation. As shown in this diagram, the output VOUT of the inverter INV3 goes to the bias voltage Vb in the AZ period and goes "H" or "L" in the COMP period, and the latch output LOUT of the latch circuit 11 shows, in the AZ period, the result of the comparison in the preceding COMP period.
While the chopper type voltage comparator operates basically as explained above, an offset voltage occurs in the comparison result if there is a mismatch in the characteristics of the inverters (amps). FIG. 37 and FIG. 38 show the principle.
The inverter INV1 which is shorted between the input and output in the AZ period is biased at the point where the voltages become equal at the input and the output. However, if the characteristic (L3) of the inverter INV3 in the next stage disagrees, even slightly, with the characteristic (L1) of the inverter INV1, the output voltage of the inverter INV3 is shifted from the bias voltage of the INV1 by VBERR.
When a transition is made from the state in which the output of the inverter INV3 is converging at (Vb+VBERR) in the AZ period to the comparison period to start the comparing operation, it is easy for the inverter INV3 to provide the result of "H" but it is difficult to provide the result of "L." As the result, as shown in FIG. 38, the latch output LOUT may change to erroneously output "H" in the AZ period in which it should originally output "L." When seen from the input side, it means occurrence of an offset voltage (VBERR). In the case of the configuration of FIG. 30 and FIG. 31, the same malfunction may occur also when there is a mismatch in input/output characteristic between the inverter INV2 and the inverter INV3.
To avoid the above-stated trouble, the individual inverters in the chopper type voltage comparator are made to have the same size, shape and orientation to produce the same characteristic. The size means the size of transistor, such as the channel length and the channel width, the shape means the configuration of the layout pattern, and the orientation means the direction of formation of the layout pattern.
Furthermore, since the inverters INV4 and INV5 in the latch circuit 11 function as amplifiers in the COMP period, they are usually formed of the same inverters as that for the inverter INV3 in the preceding stage. The offset voltage is usually reduced by using this configuration.
FIG. 39 is a circuit diagram showing a configuration of a parallel type A/D converter formed of a plurality of voltage comparators connected in parallel. As shown in this diagram, (n+1) ladder resistors LR1-LR(n+1) are provided in series between reference voltages VRT and VRB. In n voltage comparators CMP1-CMPn, the input voltage VIN is applied to one input of a voltage comparator CMPi (i=1 to n) and a reference tap voltage VRi obtained from a node between ladder resistors LRi and LR(i+1) is applied to the other input. The outputs from the voltage comparators CMP1-CMPn are provided to an encoder 12 and the encoder 12 outputs the encoded result EOUT on the basis of the outputs from the voltage comparators CMP1-CMPn.
In an A/D converter having this configuration, the voltage comparators CMP1-CMPn compare the input voltage VIN and their respective reference tap voltages VR1-VRn in parallel in synchronization with a certain clock. Then the encoder 12 encodes the comparison results from the voltage comparators CMP1-CMPn to output a digital signal, or the encoded result EOUT.
Accordingly, n=7 in the case of 3-bit A/D conversion, when the outputs of the voltage comparators CMP1-CMP3 are "L" and the outputs from the CMP4-CMP7 are "H" as shown in FIG. 39, the encoder 12 outputs "011" as the encoded result EOUT.
FIG. 40 is a circuit diagram showing a chopper type voltage comparator using differential amplifiers. In FIG. 40, the input voltage VIN and the reference voltage VREF are connected to one electrode of a capacitor C11 through switches S11 and S12, respectively. The other electrode of the capacitor C11 is connected to the first input portion of a differential amplifier AMP1. The first output of the differential amplifier AMP1 is connected to one electrode of a capacitor C12 and is also fed back to the first input through a switch S13. The other electrode of the capacitor C12 is connected to the first input portion of a differential amplifier AMP2. The first output portion of the differential amplifier AMP2 is connected to the first input portion of a differential amplifier AMP3 and is also fed back to the first input through a switch S14.
On the other hand, an inverse input voltage VIN and an inverse reference voltage VREF respectively in the opposite phases to the input voltage VIN and the reference voltage VREF are connected to one electrode of a capacitor C21 through switches S21 and S22, respectively. The other electrode of the capacitor C21 is connected to the second input portion of the differential amplifier AMP1 and the second output portion of the differential amplifier AMP1 is connected to one electrode of a capacitor C22 and is also fed back to the second input through a switch S23. The other electrode of the capacitor C22 is connected to the second input portion of the differential amplifier AMP2 and the second output portion of the differential amplifier AMP2 is connected to the second input portion of the differential amplifier AMP3 and is also fed back to the second input through a switch S24.
The output of the differential amplifier AMP3 (the first output or the second output) is provided to a latch circuit 13 and the latch output LOUT from the latch circuit 13 makes the output of the voltage comparator.
FIG. 41 is a circuit diagram showing an internal configuration of the differential amplifier AMP1 (AMP2, AMP2) formed of a differential pair of NMOS transistors. As shown in this diagram, PMOS transistors Q11 and Q12, receiving the power-supply voltage VDD at their respective sources in common and the constant voltage VPB at their respective gates in common, are connected to the drains of NMOS transistors Q13 and Q14 through nodes N11 and N12, respectively. The NMOS transistor Q13 and the NMOS transistor Q14 form a differential pair, which receives a first voltage V1 at the gate of the NMOS transistor Q13 and receives a second voltage V2 at the gate of the NMOS transistor Q14. The sources of the NMOS transistors Q13 and Q14 are grounded in common through an NMOS transistor Q15 receiving a constant voltage VBB at its gate. The drain (node N11) and the gate of the NMOS transistor Q13 are connected through the switch S13 and the drain (node N12) and the gate of the NMOS transistor Q14 are connected through the switch S23.
In the differential amplifier AMP1 having this configuration, the gate of the NMOS transistor Q13 serves as the first input portion, the node N11 as the first output portion, the gate of the NMOS transistor Q14 as the second input portion, and the node N12 as the second output portion.
FIG. 42 is a circuit diagram showing an internal configuration of the differential amplifier AMP1 (AMP2, AMP2) formed of a differential pair of PMOS transistors. As shown in this diagram, NMOS transistors Q21 and Q22, having their respective sources grounded in common and receiving a constant voltage VNB at their respective gates in common, are connected to the drains of PMOS transistors Q23 and Q24 through nodes N21 and N22, respectively. The PMOS transistor Q23 and the PMOS transistor Q24 form a differential pair, which receives the first voltage V1 at the gate of the PMOS transistor Q23 and receives the second voltage V2 at the gate of the PMOS transistor Q24. The sources of the PMOS transistors Q23 and Q24 are connected to the power-supply voltage VDD through a PMOS transistor Q25 receiving a constant voltage VPB at its gate. The drain (node N21) and the gate of the PMOS transistor Q23 are connected through the switch S23 and the drain (node N22) and the gate of the PMOS transistor Q24 are connected through the switch S13.
In the differential amplifier AMP1 having this configuration, the gate of the PMOS transistor Q23 serves as the first input portion, the node N21 as the first output portion, the gate of the PMOS transistor Q24 as the second input portion, and the node N22 as the second output portion.
The switches S11-S14 and the switches S21-S24 have the same internal configuration as the switches S1-S4 shown in FIG. 31. The switches S11, S13, S14, S21, S23 and S24 turn on when the control signal .phi. is "H" and the switches S12 and S22 turn on when the control signal it is "L."
The operation is basically the same as that of the chopper type voltage comparator shown in FIG. 30 formed of inverter amplifiers except that it handles differential signal, so it is not described again. However, it has the advantage that it is not affected by noise superimposed in the same phase because it handles differential signal, unlike the chopper type voltage comparator formed of inverter amplifiers.
Although it is ideal when forming a parallel type A/D converter as shown in FIG. 39 that the analog input and the reference voltage are both differential signals, fixed voltages may be supplied on one side, that is, instead of the inverse input voltage VIN and the inverse reference voltage VREF respectively in the opposite phases to the input voltage VIN and the reference voltage VREF and connected to the second input portion.
The conventional chopper type voltage comparator configured as explained above has the following three problems.
(1) When the frequency of the input voltage VIN, an analog signal, becomes high, the voltage VN1 at the input portion of the inverter amplifier INV1 is, in the AZ period, not fixed at the bias voltage Vb providing a good gain characteristic, but varies according to the input voltage VIN. (FIG. 43)
Hence, the comparison operation in the COMP period does not start at the high-gain bias voltage. This is equivalent to an offset in the initial value, which causes the phenomenon that one of "H" and "L" is easy to output and the other is difficult to output (offset voltage). For example, if it is set to (Vb+ERR) in the AZ period as shown in FIG. 44, the "H" level is easy to output and the "L" level is difficult to output. This may cause the latch output LOUT to output "H" when it should output "L," as shown by the dotted line in the period T22.
Preventing the input voltage VN1 to the inverter INV1 from varying with the input voltage VIN in the AZ period requires use of an inverter INV1 of larger size, leading to the necessity of use of larger inverters as the inverters INV2 and INV3 in and after the second stage, which results in an increase in the power consumption.
(2) When the capacitor C1 has voltage dependence, if the capacitance value is smaller in the COMP period than in the AZ period, the voltage change on the one electrode side (the input side) of the capacitor C1 is not correctly transferred to the other electrode side (the inverter INV1 side), which deteriorates the resolution of the voltage comparator. This may also cause distortion, for the capacitance value changes according to the input voltage VIN.
As to the voltage dependence of the capacitance, it is known that the structure shown in FIG. 45 formed of two layers of polysilicon (or metal layers) has no voltage dependence but the structure formed of an N+ diffusion layer and polysilicon shown in FIG. 46 has voltage dependence.
In FIG. 45, a first-layer polysilicon 33 and a second-layer polysilicon 34 are formed on a semiconductor substrate 35. The first-layer polysilicon 33 is connected to an input terminal 31 and the second-layer polysilicon 34 is connected to an output terminal 32. An oxide film is formed on a part (not shown) of the semiconductor substrate 35. Hence, a capacitor formation portion 36 is formed between the first-layer polysilicon 33 and the second-layer polysilicon 34.
In FIG. 46, an N.sup.+ diffusion region 38 is formed in the surface of a P.sup.+ semiconductor substrate 37 and a first-layer polysilicon 33 is formed on the semiconductor substrate 37. The input terminal 31 is connected to the N+ diffusion region 38 and the output terminal 32 is connected to the first-layer polysilicon 33. An oxide film is formed on a part (not shown) of the P.sup.30 semiconductor substrate 37. Accordingly, a capacitor formation portion 39 is formed between the N.sup.30 diffusion region 38 and the first-layer polysilicon 33.
FIG. 47 shows the voltage dependences of the capacitance values of the capacitors structured as shown in FIG. 45 and FIG. 46. In FIG. 47, L11 shows the voltage versus capacitance value change of the capacitor C1 formed of the two-layered polysilicon shown in FIG. 45 and L12 shows the voltage versus capacitance value change of the capacitor C1 having the MOS structure shown in FIG. 46. The voltage in FIG. 47 indicates a voltage at one electrode of the capacitor C1 with respect to that at the other electrode.
(3) With the latch circuit 11 (13) holding the previous comparison result at "H"or "L," the next comparison result is inputted to the latch circuit (in the amplifying process). Accordingly, as shown in FIG. 48, when the switches S1, S3, S4 and SL2 change from on to off and the switch S2 and the switch SL1 change from off to on, the previous held data operates in such a direction as to prevent the voltage change of the next captured input data toward "H" or "L" (kickback), which deteriorates the accuracy of the voltage comparator.
For example, as shown in FIG. 49, if the latch output LOUT at "H" is outputted in the AZ period of the period T23, the output VOUT of the inverter INV3 may not be lowered enough in the COMP period in the following period T24, possibly causing the latch output LOUT to erroneously output "H" in the AZ period in the period T24.